1. Field of the Invention
The present invention relates to the field of 3-dimensional stacked substrates and semiconductor packaging.
2. Discussion of Related Art
Three-dimensional stacked substrate (3D-SS) arrangements are electronic devices having a plurality of stacked semiconductor die/chips/wafers that are physically and electrically interconnected with one another. The drive toward achieving 3D-SSs is in its infancy, and numerous technical problems for achieving 3D-SSs have not yet been satisfactorily resolved.
Techniques similar to those used for a 3D-SS may also be used in physically and electrically connecting a die or 3D stack of die to a package substrate.
With each generation, as devices operate at lower voltages and higher frequencies, current levels at the die—die and/or at the die-package interface are increasing. This may cause EM (electromigration) failure for a 3D-SS at the die—die interface, or may cause EM failure at the die-package interface.